View ACS760ELF-20B_6552495.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the acs760 combines allegro ? hall-effect current sense technology with a hot-swap controller resulting in a more efficient integrated controller for 12 v applications. by eliminating the need for a shunt resistor, the i 2 r losses in the power path are reduced. when the acs760 is externally enabled, and the voltage rail is above the internal uvlo threshold, the internal charge pump drives the gate of the external fet. when a fault is detected, the gate is disabled while simultaneously alerting the application that a fault has occurred. the integrated protection in the acs760 incorporates three levels of fault protection, which includes a power fault with user-programmable delay, a user-programmable overcurrent fault threshold with programmable delay, and short circuit protection, which disables the gate in less then 2 s. additionally, in the event the external high-side fet fails short, the acs760 detects the s1 short failure and immediately disables the gate and alerts the host system. unlike the three protection faults, cycling the en pin does not reset the s1 short failure. power to the device must be cycled. 760elf20b-ds, rev. 8 features and benefits ? hall-effect current monitor?no external sense resistor required ? analog output voltage (factory trimmed for gain and offset) proportional to applied current ? external high-side fet gate drive ? 240v*a power fault protection with user-programmable delay ? user programmable overcurrent fault protection with programmable delay ? 1.5 m internal conductor resistance ? short circuit protection isolates failed supply from output in < 2 s ? active low fault indicator output signal ? external fet failure detection with active low s1 short failure indicator output signal ? user controlled soft start / hot-swap function ? logic enable input pin ? 10.8 to 13.2 v, single-supply operation ? 2 kv esd protection for all pins 12 v high-side hot-swap hall effect based current monitor ic package: 24 pin qsop (suffix lf) typical application approximate scale ACS760ELF-20B ip? ip? ip? ip? ip? ip? gate gnd fb? fb+ s1short fault 1 2 3 4 5 6 7 8 9 10 11 12 ip+ ip+ ip+ ip+ ip+ ip+ en viout iset cg ocdly opdly 24 23 22 21 20 19 18 17 16 15 14 13 acs760 s1 d1 1 k 1 k i p backplane v load r fault r fb r g c load r s1 3.3 v c opd c ocd c g c en r set r en v out enable c in rv1 v s_in v s_ret a a b b c c rv1 is required only for inductive loads. d1 should be a schottky for inductive loads, to eliminate over-stress of the acs760. fb? is tied to gnd at the point of load.
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number package packing* acs760elftr-20b-t qsop24 surface mount 2500 pieces/reel *contact allegro for additional packing options absolute maximum ratings characteristic symbol notes rating units forward voltage, ip x pins* v cc 24 v gate drive output voltage* v gate 32 v fb+ forward voltage* v fb+ 24 v en forward voltage* v en 32 v all other pins forward voltage v in 8v reverse dc voltage, all pins* v r ?0.5 v reverse transient dc voltage, all pins* v r 10 s pulse ?5 v current level output current source i viout(source) 1ma current level output current sink i viout(sink) 1ma operating ambient temperature t a range e ?40 to 85 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 170 oc * with respect to gnd.
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list table number name function 1-6 ip+ primary sampled current conduction path input; power input pins: connected to v cc 7 en enable pin. toggling this pin to the low state after a fault condition resets the acs760. 8 viout analog current level output. output voltage on this pin is proportional to the current flowing from the ip+ pins to the ip? pins. 9 iset terminal for r set resistor. sets fault current threshold, i pf , via external resistor, r set , connected between this terminal and gnd. factory trimmed 100 a current source flows out of this pin. 10 cg terminal for c g capacitor. may be used to adjust the turn-on time and soft start control of an external mosfet, s1. voltage on this pin limits inrush current through mosfet s1. set via external capacitance, c g , connected between this pin and gnd. this capacitor is charged by an internal 20 a current source. 11 ocdly terminal for external capacitor, c ocd , used to adjust delay for overcurrent shutdown, set via the external capacitor, c ocd , connected between this pin and gnd. 12 opdly terminal for external capacitor, c opd , used to adjust delay for overpower shutdown, set via the external capacitor, c opd , connected between this pin and gnd. 13 f a u l t active low; output signal for short circuit and 240 v*a overload faults; does not trip for s1 short circuit fault. connect a 1 k pull-up resistor between this pin and the 3.3 v rail. 14 s1short active low; output signal for mosfet s1 failure. connect a 1 k pull-up resistor between this pin and the 3.3 v rail. 15 fb+ input of positive feedback on output voltage. used to determine 240 v*a threshold by difference between fb+ and fb? pins. 16 fb- input of negative feedback on output voltage. used to determine 240 v*a threshold by difference between fb+ and fb? pins. pulling the fb? pin to 3.3 v, and the opdly pin to gnd, disables the 240 v*a power fault, which allows the acs760 to operate purely in current mode. 17 gnd terminal for ground connection. 18 gate terminal for external mosfet, s1. provides output voltage to drive s1. current through s1 is controlled at start-up by external capacitance connected between the cg pin and gnd. 19-24 ip? primary sampled current conduction path output; power output pins. pin-out diagram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ip? ip? ip? ip? ip? ip? gate gnd fb? fb+ s1short fault ip+ ip+ ip+ ip+ ip+ ip+ en viout iset cg ocdly opdly
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram + ? + ? power calculator short circuit detection zero current output voltage adjustment signal recovery dynamic offset cancellation charge pump hall current drive gate s1 fb+ fb? iset on opdly ocdly opdly +12 v in ocdly bias and v reg viout cg en ip+ ip ? uvlo fault logic 100 k +12 v load fault s1short
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics valid at v cc = 12 v, t a = 0c to 85c, unless otherwise noted characteristic symbol test conditions min. typ. max. units general electrical characteristics linear sensing range i p current flows from ip+ to ip- pins 0 ? 55 a primary conductor resistance r primary t a = 25c ? 1.5 ? m supply voltage v cc voltage applied to ip+ pins ? 12 ? v supply current i cc ?1012ma undervoltage lockout (uvlo) v uvloh v cc rising and cg pin current source turns on, en pin = high ? ? 10.5 v v uvlol v cc falling and cg pin current source turns off, en pin = high 7.1 ? ? v uvlo delay to chip enable/ disable t uvloe enabling, measured from rising v cc > v uvloh to v gate > 1 v ? 500 900 s t uvlod disabling, from falling v cc < v uvlol to v gate < 1 v ? ? 2 s fb+ to fb? input resistance r fb t a = 25c ? 240 ? k current sense performance characteristics viout analog output propagation time t prop t a = 25c, i p = 0 20 a, capacitance from viout to gnd = 100 pf ?2? s viout analog output 10-90% rise time t r t a = 25c, i p = 0 20 a, capacitance from viout to gnd = 100 pf ?5? s viout analog signal bandwidth 1 f 3db ?3 db, ip = 10 a peak-to-peak, t a = 25c, no external device filter, capacitance from viout to gnd = 100 pf ? 50 ? khz viout analog signal sensitivity sens t a = 25c ? 65 ? mv/a over full ambient operating temperature range 61.5 ? 67.5 mv/a t a = 25c ? 5.416 ? mv/g over full ambient operating temperature range 5.275 ? 5.558 mv/g sensitivity slope over temperature ? sens ta t a = 0c to 25c ? 0.042 ? mv/a/c t a = 25c to 85c ? 0.027 ? mv/a/c viout analog noise level v noise(pp) mean peak-to-peak, t a = 25c, 50 khz external device filter ? 20 ? mv viout analog nonlinearity e lin over full ambient operating temperature range and linear sensing range ? 0.5 2.0 % zero current output voltage v iout(q) t a = 0c to 55c 0.38 ? 0.42 v t a = 0c to 85c 0.37 0.4 0.43 v zero current output slope over temperature ? i out(q)ta t a = 0c to 25c ? ?0.148 ? mv/c t a = 25c to 85c ? ?0.057 ? mv/c output voltage saturation limits 2 v ol t a = 25c ? 0.25 ? v v oh t a = 25c ? 3.6 ? v viout total error % of i p e tot t a = 25c, i p = 20 a ? 1.0 ? % t a = 0c to 85c, i p = 20 a ? ? 3.5 % viout dc output resistance r viout i viout = 1 ma ? 1 ? current fault performance characteristics load power fault threshold p f(th) 222 230 238 w 240 v*a fault signal delay t pfh t a = 25c, measured from fault signal to v gate < 1 v, 2.2 f capacitance from opdly pin to gnd, load step from 17 a to 23 a in 100 ns ? 425 ? ms t pfl t a = 25c, measured from fault signal to v gate < 1 v, opdly pin open, load step from 17 a to 23 a in 100 ns ?1012 s 240 v*a fault signal delay drift ? t pf over full operating ambient temperature range, external capacitor with 5% tolerance ?15 ? 15 % internal ?3 db filter frequency for fb+ and fb? pins f fbfilt t a = 25c ? 50 ? khz continued on the next page?
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i p fault switchpoint tolerance 3 e pf percentage error of i pf ?15 ? 15 % i pf fault signal delay 4 t ipflmax measured from fault signal to v gate < 1 v, ocdly pin open, load step from 17 a to 45 a in 100 ns ?812 s t ipfh measured from fault signal to v gate < 1 v, 2.2 nf capaci- tance from ocdly pin to gnd, load step from 17 a to 45 a in 100 ns ? 425 ? s maximum short circuit/overcurrent fault threshold 5 i sc 60 110 160 a short circuit/overcurrent fault gate delay t sc measured from fault signal to v gate < 1 v, includes t gf ?23 s voltage fault performance characteristics internal pull down resistance between en and gnd r en t a = 25c ? 100 ? k en voltage threshold 6 v enh ic enabled when v en > v enh 1.93 ? ? v v enl ic disabled when v en < v enl ??1v s1 short circuit detection current 7 i s1s ic enabled or disabled 0.9 1.5 2.1 a s1 short circuit detection delay t s1s measured from disablement of the device to detection of an s1 fault ??45 s s1short output voltage v s1sol i s1short = 3 ma sink current ? ? 0.4 v s1short output leakage current i s1sih v s1short = 3.3 v ? ? 5 a fault output voltage v faultol i fault = 3 ma sink current ? ? 0.4 v fault output leakage current i faultih v fault = 3.3 v ? ? 5 a gate drive performance characteristics internal charge pump voltage v cp t a = 25c ? v cc + 10 ? v average gate drive current i gd v cc = 12 v, t a = 25c 25 50 ? a charge pump switching frequency f cp t a = 25c ? 1 ? mhz gate rise time t gr t a = 25c, external mosfet s1 gate capacitance = 5.8 nf, measured from v gate = 0 v to 15 v, cg pin open, no output load capacitance ?1?ms t a = 25c, external mosfet s1 gate capacitance = 5.8 nf, measured from v gate = 0 v to 15 v, 3.75 f capacitor con- nected between cg and gnd pins ? 500 ? ms gate sink resistance r gsink ?2030 gate discharge current i gd v gate = v cc + 10 v ? 1000 ? ma gate shutdown delay t gsd measured from fault event to start of gate pull down ? 200 ? ns gate maximum fall time t gf measured from v gate = 90% of maximum to v gate < 1 v, external mosfet s1 gate capacitance = 5.8 nf. en pin switched from high to low, fault or s1short signal ? 800 ? ns cg output current i slew t a = 25c 18 20 22 a 1 the small signal, ac bandwidth of this device is approximately 90 khz. 2 this test requires currents sufficient to swing the output driver between the fully off state and the saturated state. assumes that the viout pin is con- nected to an analog-to-digital converter that saturates at 2.5 v. the viout signal is linear above 2.5 v, however, this test is not intended to indicate a range of linear operation. 3 assumes that a 1% resistor with a flat temperature coefficient is connected between the iset and gnd pins. 4 can exceed t ipfh (max) delay period via the use of a larger external capacitor. voltage trip point on the high side of the capacitor is 3.85 v. 5 this parameter is internally programmed and cannot be controlled by the end user. 6 the fault output signal is latched. after a latched fault event, the device will be reset only when either: (a) v en drops below v enl , or (b) the power to the device (applied to the ip+ pins) is toggled off and then back on. 7 the voltage on the gate of the external mosfet s1 does not need to be < 1 v in order for the device to detect an s1 short circu it condition. the device does detect a faulty s1 when the gate of s1 is shorted to the s1 source or drain terminal. operating characteristics, (continued) valid at v cc = 12 v, t a = 0c to 85c, unless otherwise noted characteristic symbol test conditions min. typ. max. units
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com soft start and fault characteristics gate turn on rise time, t gr . set by external capacitance, c g , on the cg pin, such that c g = 7.5 t gr , where c g is in ? f and t gr is rise time in seconds. for example, a 3.9 ? f capacitor connected from the cg pin to gnd (without an output load) will yield a rise time of approximately 500 ms: c g ? 7.5 0.5 s = 3.75 ? f, ? 3.9 ? f (a common capacitor value). when the cg pin is kept open, the acs760 has a minimum t gr of 1 ms typical. i pf fault signal delay, t ipf . this is the delay from high current level fault sense to the start of turn-off of the external mosfet s1 turn-off. set by external capacitance, c ocd , on the ocdly pin, such that c ocd = 5.17 t rocd ; where c ocd is in ? f and t rocd is rise time in seconds. when the ocdly pin is kept open, the ic has a minimum fault delay, t ipflmax , of 8 ? s maximum. load power fault signal delay, t pfl . this is the delay from maximum power level fault, p f(th) , sense to the start of external mosfet s1 turn-off. set by external capacitance, c opd , on the opdly pin, such that c opd = 5.17 t ropd ; where c opd is in ? f and t ropd is rise time in seconds. the ic has a minimum fault delay when the opdly pin kept open of 10 ? s typical. i pf fault current setting, i pf . the i pf upper trip level may be set by using a resistor between the iset pin and gnd, such that r set = 10 4 (0.4 + 0.065 i pf ), where i pf is in a and r set in ? . accuracy characteristics sensitivity, sens. the change in device output in response to a 1 a change through the primary conductor. sens is the product of the magnetic circuit sensitivity (g/a) and the linear ic amplifier gain (mv/g). the linear ic amplifier gain is trimmed at allegro final test to optimize the sensitivity (mv/a) for the full-scale cur- rent range of the device. noise, v noise(pp) . the product of the linear ic amplifier gain (mv/g) and the noise floor for the allegro hall effect linear ic. dividing the noise (mv) by the sensitivity (mv/a) provides the smallest current that the device is able to resolve. nonlinearity, e lin . the linearity of the v iout signal is the degree to which the voltage output from the device varies in direct proportion to the primary sensed current, up to 20 a. nonlinearity reveals the maximum deviation in the slope of the device transfer function compared to the slope of the ideal trans- fer curve for this transducer. the following equation is used to derive the linearity: 100 1? [ { [ { ( v iout _full-scale amperes ? v iout(q) ) 2 ( v iout _half-scale amperes ? v iout(q) ) , where full-scale current is 20 a, and half-scale current is 10 a. zero current output voltage, v iout(q) . the output of the device when the primary current, i p , is 0 a. variation in v iout(q) can be attributed to the resolution of the allegro linear ic quies- cent voltage trim and thermal drift. v iout total error, e tot . the maximum percentage deviation of the actual output from its ideal value, based on an ideal sensitiv- ity of 65.7 mv/a at 25c and 64.3 mv/a at 85c. dynamic response characteristics propagation delay, t prop . the time required for the device output to reflect a change in the primary current signal. propaga- tion delay is attributed to inductive loading within the linear ic package, as well as in the inductive loop formed by the primary conductor geometry. propagation delay can be considered as a fixed time offset and may be compensated. primary current transducer output 90 0 i (%) response time, t response t primary current transducer output 90 10 0 i (%) rise time, t r t rise time (t r ). the time interval between a) when the device reaches 10% of its full scale value, and b) when it reaches 90% of its full scale value. the rise time to a step response is used to derive the bandwidth of the device, in which ?(?3 db) = 0.35 / t r . both t r and t response are detrimentally affected by eddy current losses observed in the conductive ic ground plane. response time, t response . the time interval between a) when the primary current signal reaches 90% of its final value, and b) when the device reaches 90% of its output corresponding to the applied current. primary current transducer output 90 0 i (%) propagation time, t prop t
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 240 v*a fault operation the timing diagram in figure 1 shows characteristic operation of the acs760 when the power consumed from the 12 v system bus exceeds a 240 v*a or 240 w level. the system power supply bus reaches the nominal steady state level of 12 v before the en pin (enable pin, active high) of the acs760 transitions to the high state at time t en1 . note that, when the en pin is in the low state, the gate pin is actively pulled low. however, as shown in the timing diagram, the voltage on the gate pin increases with a positive slope after the en pin transitions to the high state. the ramp rate of the gate pin is controlled by the value of the capacitor connected to the cg pin. at a certain gate voltage, current begins to flow through the external protection mosfet, s1, and this current increases as the gate voltage increases. the voltage at the viout pin, which is the current device output voltage of the acs760, proportionally tracks the current that flows through the mosfet. in the timing diagram, the system is in normal, steady state opera- tion up until the time t init_f . at t init_f , the current load on the 12 v power supply increases from 19.2 to 22 a and the acs760 internally registers a 240 v*a fault condition. at this time, the voltage on the opdly pin increases with a constant slope. (this slope is controlled by the value of the capacitor connected to the opdly pin). this voltage continues to increase with a constant slope until either: ? the opdly pin voltage reaches a threshold of 3.85 v (if this occurs, the fault signal is latched in the low state), or ? the power consumption of the system falls below 240 v*a (at which time the opdly pin voltage is pulled to ground) a 240 v*a fault event is detected at t 240va_f . at this time, the fault signal transitions to the low state and the gate pin is pulled to ground. the fault signal is latched and the chip will pull down the gate voltage until the en pin of the acs760 transitions to the low state and then back to the high state. as shown in the timing diagram, certain acs760 signals (the fault signal and the opdly pin voltage) are reset when the en pin transitions to the low state. these signals are reset in order to guarantee normal device operation (soft start and fault monitor- ing) when the en signal transitions back to the high state. 0.4 v 0.4 v 1.83 v v iout voltage load current / i p gate voltage fault en cg pin voltage v load to load opdly pin voltage ocdly pin voltage 12 v on ip+ pins 22 a 1.648 v 22 v 19.2 a 12 v 3.85 v threshold 3.3 v 5.5 v 3.3 v 5.5 v 0 a 0 v 0 v 0 v 0 v 0 v 12 v t en1 t reset time t init_f t 240va_f 0 v figure 1. timing diagram for 240 v*a fault
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com soft short circuit fault operation the timing diagram in figure 2 shows the characteristic opera- tion of the acs760 when the current load on the 12 v system bus jumps from the 19 to 20 a level to the 40 a level. the 40 a load is typically indicative of a soft short circuit on the i load side of the external mosfet. in figure 2, the system power supply bus reaches the nominal steady state level of 12 v before the en pin (enable pin, active high) of the acs760 transitions to the high state at time t en1 . note that when the en pin is in the low state, the gate pin is actively pulled low. however, as shown in the timing diagram, the voltage on the gate pin increases with a positive slope after the en pin transitions to the high state. the ramp rate of the gate pin is controlled by the value of the capacitor connected to the cg pin. at a certain gate voltage, current begins to flow through the external protection mosfet, s1, and this current increases as the gate voltage increases. the voltage at the viout pin, which is the current device output voltage of the acs760, proportionally tracks the current that flows through the mosfet. in the timing diagram the system is in normal, steady state operation up until the time t init_f . at t init_f the current load on the 12 v power supply increases from 19.2 a to 40 a and the acs760 internally registers both a 240 v*a fault condition and an i pf fault condition. in this example, the i set voltage was set at 3.0 v, which corresponds to a 40 a fault threshold. at t init_f , the voltage on the opdly and ocdly pins increases with a constant slope. the slope of the voltage on the two delay pins is controlled by the value of the capacitor connected to each pin. in this case the capacitor on the ocdly pin is smaller than the capacitor on the opdly pin and the voltage on the ocdly pin ramps much faster than the voltage on the opdly pin (both pins are connected to separate 20 a current sources). the voltages on each delay pin continues to increase with a constant slope until either: ? either the opdly or the ocdly pin voltages reach a threshold of 3.85 v (if this occurs, the fault signal is latched in the low state), or ? the current load of the system falls below 20 a for the opdly pin and 40 a for the ocdly pin in figure 2 a short circuit fault event is detected at t 40a_f . at this time, the fault signal transitions to the low state and the gate pin is pulled to ground. the fault state is latched and the chip will pull down the gate voltage until the en pin of the acs760 transitions to the low state and then back to the high state. as shown in the timing diagram, certain acs760 signals (the fault signal and the ocdly pin voltage) are reset when the en pin transitions to the low state. these signals are reset in order to guarantee normal device operation (soft start and fault monitoring) when the en signal transitions back to the high state. 0.4 v 0.4 v 3 v v iout voltage load current / i p gate voltage fault en cg pin voltage v load to load opdly pin voltage ocdly pin voltage 12 v on ip+ pins 40 a 1.648 v 22 v 19.2 a 12 v 3.85 v threshold 3.85 v threshold 3.3 v 5.5 v 3.3 v 5.5 v 5.5 v 0 a 0 v 0 v 0 v 0 v 0 v 12 v t en1 t reset time t init_f t 40a_f 0 v figure 2. timing diagram for 30 to 40 a load fault
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 3. (a) timing diagram for a 50 m short circuit from v load to gnd; (b) timing diagram for a 50 m short circuit from v load to gnd, capacitor c ocd with high rating connected. hard short circuit (50 m from v load to gnd) fault operation the timing diagram below specifically shows characteristic operation of the acs760 when the device is powered on (via the en pin) and a 50 m ? short circuit is present from load side of the external mosfet, s1, to ground. in figure 3 the system power supply bus reaches the nominal steady state level of 12 v before the en pin of the acs760 tran- sitions to the high state at time t en1 . the voltage on the gate pin increases with a positive slope after the en pin transitions to the high state. the ramp rate of the gate pin is controlled by the value of the capacitor connected to the cg pin. in the example shown below a small capacitor is connected to the cg pin and the pin ramps to 5.5 v in < 10 ? s. in panel a of figure 3, the device is enabled into a 50 m ? short circuit. therefore, as the gate voltage increases the current through the external mosfet increases at a rapid rate. in this example case it is assumed that there is no capacitor on the ocdly pin. when the current through the mosfet exceeds the threshold set by the r set resistor, the voltage on the ocdly pin rises quickly beginning at t 40a_f . as the voltage on the ocdly pin rises, so does the voltage on the cg pin and the current through the external mosfet. if there is no capacitor on the ocdly pin, and if the acs760 short circuit fault threshold, i sc , is greater than 100 a, then the ocdly pin will reach the 3.85 v threshold before the current through the external mos- fet exceeds i sc . this is the case depicted in the panel a. the fault event is detected at t gate_low . at this time. the fault signal transitions to the low state and the gate pin is pulled to ground. in the event that a large capacitor is connected to the ocdly pin, the acs760 will not pull down the gate of the external mos- fet until the current flowing through the mosfet exceeds i sc (shown in panel b, under the assumption that i sc equals 130 a). the device pulls down the mosfet gate approximately 2 ? s after the load current exceeds this threshold. if a large capacitor is connected to the ocdly pin a significant current (> 40 a but < 160 a) may flow through the mosfet for tens of microsec- onds before the short circuit fault threshold trips. these tens of microseconds elapse as the gate charges and the load current increases, finally exceeding the short circuit threshold. the fault signal is latched and the chip will pull down the gate voltage until the en pin of the acs760 transitions to the low state and then back to the high state. certain acs760 signals (soft start and fault monitoring) are reset when the en pin transi- tions to the low state. these signals are reset in order to guarantee normal device operation when the en signal transitions to the high state. (a) (b) 0.4 v 0.4 v 5.25 v v iout voltage load current / i p gate voltage fault en cg pin voltage v load to load opdly pin voltage ocdly pin voltage 12 v on ip+ pins 40 a 100 a 1.648 v 22 v 19.2 a 12 v 3.85 v threshold 3.85 v threshold 3.3 v 5.5 v 3.3 v 5.5 v 5.5 v 0 a 0 v 0 v 0 v 0 v 0 v 12 v t en1 t reset time t gate_low t 40a_f 0 v 0.4 v v iout voltage load current / i p gate voltage fault en cg pin voltage v load to load opdly pin voltage ocdly pin voltage 12 v on ip+ pins 40 a 130 a 3.85 v threshold 3.85 v threshold 3.3 v 0 a 0 v 0 v 0 v 0 v 0 v 12 v t en1 t reset time t gate_low_in < 2 s t 130a_f t 40a_f 0 v
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com s1 short fault operation the timing diagram in figure 4 shows the characteristic operation of the acs760 when the power consumed from the 12 v system bus exceeds a 240 v*a or 240 w level. for the operation during a 240 v*a fault condition, refer to figure 1. that section describes the operation of the acs760 until the time t 240va_f . figure 4 depicts a 240 v*a fault, but continues on to demonstrate the abil- ity of the acs760 to detect damage and improper operation of the external mosfet in an s1 short circuit event. at t 240va_f , the fault signal transitions to the low state and the acs760 pulls down the voltage on the gate pin. during normal operation, when the gate pin is at 0 v, the current through the s1 mosfet (and therefore through the acs760) equals approxi- mately 0 a. however, in the case depicted in figure 4, current through the s1 mosfet flows even though the gate pin is pulled low. if a fault has occurred and more than 2.1 a flow through the acs760, then the s1short signal transitions to the low state. when the s1short signal is low, that indicates to the system that the acs760 cannot turn off the external mosfet (for example, when a short circuit exists between the source and the drain of the mosfet). in the case depicted, the system shuts down the 12 v power supply after the s1short signal transi- tions to the low state. note that, in some cases, the gate of the s1 mosfet may be shorted to the source or drain of the mosfet. in this case the acs760 may not be able to pull down the gate of the s1 mos- fet. however, in this case the acs760 will still register an s1 short even if the gate potential is equal to or greater than 12 v. if the acs760 is disabled (en pin in the low state) and greater than 2.1 a flows through the acs760, then the device will reg- ister an s1 short condition and the s1short pin will transition to the low state. the voltage on the gate pin is not used as a determining factor when sensing an s1 short condition. the s1short signal will not reset to a high state until power to the device is cycled. toggling the en pin does not reset the latched s1 short state. determining the root cause of an acs760 fault event the following truth table provides system debugging information in the event of a fault event during use of the acs760. note that for all of the fault conditions listed, it is possible to monitor the voltages of various acs760 output pins and determine the cause of the acs760 fault event. 0.4 v v iout voltage load current / i p gate voltage fault en cg pin voltage v load to load opdly pin voltage ocdly pin voltage 12 v on ip+ pins s1short pin 22 a 3 a 1.83 v 12 v 3.85 v threshold 3.3 v 3.3 v 0 a 0 v 0.4 v 0.4 v 0.4 v 3.3 v 5.5 v 5.5 v 0 a 0 v 0 v 0 v 0 v 0 v 0 v 0 v 0 v 12 v t en1 t reset time t 240a_f t s1short t init_f 0 v figure 4. timing diagram for s1 short fault condition truth table pin logic state probable root cause fault pin opdly pin ocdly pin low high low 240 v*a system power level, p f(th) , exceeded low don?t care high i p fault current threshold, i pf , exceeded low low low short circuit fault threshold, i sc , exceeded
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 12 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fault condition characteristics figure 5. 240 v*a fault: with v cc = 12 v and acs760 enabled, apply load figure 6. i pf event: with v cc = 12 v and acs760 enabled, apply load figure 7. hot-swap with 1 f capacitor from cg pin to gnd, resistive load approximately 0.17 . capacitive load approximately 3300 f; c g capacitor limits inrush current to 720 ma during hot swap event (15 a current probe used) gate opdly input current 10 mv/a fault gate ocdly input current 10 mv/a fault enable gate viout ipout
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 13 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 8. power-up: with the enable jumper on, apply v cc figure 9. power-up: with v cc on, apply the enable jumper (enables acs760) figure 10. power-down: with enable jumper on, remove supply (disables acs760) figure 11. power-up to power-down (a): remove enable jumper (disables acs760, but v cc and v iout stay high (see figure 12) figure 12. power-up to power-down (b): with acs760 disabled (see figure 11), remove supply (v cc and v iout brought low) enable gate viout vin enable gate viout vin enable gate viout vin enable gate viout vin enable gate viout vin
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 14 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com current mode operation the acs760 has the ability to operate in pure current mode. if the allegro acs760 detects power in excess of 240 v*a, the fault output of the device transitions from a logic high to a logic low level and the integrated gate driver circuitry pulls the gate of an external mosfet to gnd. the delay between the detection of an excess power condition and gate shutdown is set by an external capacitor on the opdly pin to gnd. the acs760, however, has the ability to override the power mode fault condition to operate in pure current mode. pulling the opdly pin to gnd, disables the 240 v*a power fault to allow the acs760 to operate in pure current mode. the user may then set the current fault threshold by adjusting the resistor value from the iset pin to gnd. if the current exceeds the set threshold, the fault output of the device trips and the gate of the external mosfet is pulled to gnd. the delay between the detection of a soft short circuit condition and gate shutdown is set by the capacitor on the ocdly pin. in current mode operation, the acs760 has the ability to detect a s1 short and hard short. filtering in applications where the fault and s1short pins are pulled-up prior to providing power to the device, be sure to add an rc filter with the pull-up resistor closest to the fault and s1short pins. this will ensure that the acs760 s1 short and fault logic levels remain proper under this application condition. see diagram below. ip? ip? ip? ip? ip? ip? gate gnd fb? fb+ s1short fault 1 2 3 4 5 6 7 8 9 10 11 12 ip+ ip+ ip+ ip+ ip+ ip+ en viout iset cg ocdly opdly 24 23 22 21 20 19 18 17 16 15 14 13 acs760 s1 d1 1 k 1 k 100 k 10 nf i p backplane v load r fault r fb r g c load r s1 3.3 v 3.3 v c opd c ocd c g c en r set r en v out enable c in rv1 v s_in v s_ret a a b b c c rv1 is required only for inductive loads. d1 should be a schottky for inductive loads, to eliminate over-stress of the acs760. fb? is tied to gnd at the point of load. 100 k 10 nf application information
12 v high-side hot-swap hall effect based current monitor ic ACS760ELF-20B 15 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lf, 24-pin qsop 0.635 bsc 0.25 0.15 0.25 max 1.75 max 8o 0o 1.27 0.41 0.25 bsc 1.04 ref 8.66 0.10 3.91 0.10 0.30 0.20 5.99 0.20 c 0.20 24x seating plane c 0.635 2.30 5.00 0.40 2 1 24 gauge plane seating plane a c c b a for reference only, not for tooling use (reference jedec mo-137 ae) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b reference pad layout (reference ipc7351 sop63p600x175-24m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances terminal #1 mark area pcb layout reference view standard branding reference view n = device part number t = temperature code lf = (literal) package type a = amperage tlf-aaa lllllllllll nnnnnnnnnnnnn branded face branding scale and appearance at supplier discretion copyright ?2006-2013, allegro microsystems, llc the products described herein are manufactured under one or more of the following u.s. patents: 5,619,137; 5,621,319; 6,781,359 ; 7,075,287; 7,166,807; 7,265,531; 7,425,821; or other patents pending. allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

▲Up To Search▲

Price & Availability of ACS760ELF-20B

	To Download ACS760ELF-20B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .